Thank you for your feedback. Course interleaving is enabled with the memory controller mapping to multiple address regions. I'm learn about AMBA 3. The simplified AXI4 Master Protocol supports pipelined requests, so it is not required to wait for the wr_complete signal to be high before issuing a subsequent write request. The AMBA AXI-4 Master is designed in this project, which is modeled in Verilog and simulation results for read/write operation for data/address are shown in VCS tool. Of course it can have a larger addressing space, but again it has to be in the multiples of 4KB. In practice, removing write interleaving from this part of the AMBA standard makes certain aspects of the AXI protocol easier to handle. QoS, Write Data Interleaving, unaligned data transfer, byte invariance. AXI4 supports QoS, AXI3 does NOT suppor QoS. CoreAXI4Interconnect is a configurable core with the following features: • Supports high-bandwidth and low-latency designs. 7. Where interleaving is supported, the WID and RID signals will indicate which of the interleaved transactions the data transfer relates to. Simran Sarai 2014. The Advanced eXtensible Interface ( AXI) is an on-chip communication bus protocol and is part of the Advanced Microcontroller Bus Architecture specification (AMBA). The bandwidth is measured as (number of bytes transferred in an interval)/ (latency). This feature was retracted by AXI4 protocol. sequence_length This site uses cookies to store information on your computer. v : AXI central DMA engine rtl/axi_cdma_desc_mux. Transaction address will be randomly selected based on system address map. We use the MIGs AXI4 interface. Most AXI3 masters do not support write interleaving. AXI nonblocking crossbar interconnect with parametrizable data and address interface widths and master and slave interface counts. but i have two questions about AXI afterPrefix A Denotes global Advanced eXtensible Interface (AXI) signals: Prefix AR Denotes AXI read address channel signals. 17. #- Check that the Interconnect is forwarding the correct write data with respect to address issued. Verification IP (VIP) supports all four types of atomic transactions:. 1. The slave declares a write data interleaving depth that indicates if the interface can accept interleaved write data from sources with different AWID values. Chip Select Interleaving controls how these four chip selects are interleaved within the memory controller. Thank you. You will see that wvalid is indeed changing while tready is low which is against the AXI specification. Palette data can be RGB or YUV. int attribute. All five transaction channels use the same VALID/READY handshake process Interleaving allows you to send WID transfers for a number of outstanding AW transfers, BUT. Faculty of Applied Science. esign and. here is the part axi slave rtl generated by vivado. This is to simplify the address decoding in the interconnect. e. AXI Write Address. fpga b. you told me that the interleaving is a concept only for write. emory. 15. A single instance of the AXI NoC IP can be configured to include one, two, or four instances of the integrated MC. request regardless if the request was a write or a read. note: Both the masters are accessing the same slave. By working with the master and slave devices, the AXI protocol works across five addresses that include read and write address, read and. Features of AXI 5 Channels (Write address, Write data, Write Response, Read data/response, Read address ) No strict timing relationship between address and data signal On chip, Point to Point Communication protocol Multiple Outstanding(Multiple request) Burst based transactions with only start address issued Aligned and non-aligned address support Out of order Data interleaving Atomicity. Allows for parallel read and write transactions. One major up-dation seen in AXI is that, it includes information on the use of default signaling andSupports multiple outstanding transactions: * Supports connected masters with multiple reordering depth (ID threads). AXI BRAM. the data interleaving is responsible for slaves and the write data interleaving is responsible for masters. D11 D21 D22 D12 D23 D31 D13. Write Data Interleaving in AXI. Allows reads to bypass writes, in contrast to axi_to_mem, however needs more hardware. AXI3 master devices must be configured as if connected to a slave with a Write interleaving depth of one. ased. value on the address channel. Interleaving as a study method means learning more than one subject or skill and switching between them. AXI specs in fact talks only about point to point communication, ie. The removal of write interleaving makes. Stage 4: Read Calibration Part Two—Read Latency Minimization 1. [AXI spec - Chapter 8. The AXI protocol enables: address information to be issued ahead of the actual data transfer support for multiple. No. This covergroup is hit when address phase completion of four transactions are observed in a specific combination as described above. AXI3 supports write interleaving. Recently, I read "AMBA AXI Protocol. pdf". In the case illustrated in. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed. 0 AXI. In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. There are 5 channels in AXI and each one is independent of the other. Prefix B Denotes AXI write response channel signals. Appendix A Comparison with the AXI4 Write Data Channel Read this for a description of the key differences between the AXI4-Stream interface and the AXI4 write data channel. It uses a second AXI VIP configured in slave mode with a memory model and using the AXI4 protocol to simulate a BRAM. AXI4 QoS signals do not influence arbitration priority. Newest. the AXI3 spec described the following (seen in all AXI spec releases up to and including version F). You say just an out-of-order responses by the interleaving. In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. Copyright © 2003-2010 ARM. In the AXI protocol, can you help me understand in depth about the multiple outstanding addresses, out-of order completion and data interleaving Scenario 1: There is Only 1 AXI master (with support of only 1 Master ID) doing transaction to a slave which is capable of handling multiple outstanding addresses. "AXI3 supports write interleaving. ° Write interleaving: This feature was retracted by AXI4 protocol. 4) is the case of the interleave but AXI4 does not permit the write interleaving. i understood that read transactions enable interleaving. Set slave and controller specific parameters. Address register – It contains the address to specify the desired location in memory. AXI Interconnect Product Guide v2. The DQ bits are bi-directional and have a bus turnaround time associated when switching direction. • AXI Clock Converter connects one AXI memory-mapped master to one AXI memory-mapped slave operating in a different clock domain. AHB supports the locked transfer. Address/Control is issued ahead of actual data transfer. close to full bandwidth in the interleaved output stream, and maybe also in one of the input-streams, assuming the rest are slow), then we need to FIFO-buffer data corresponding to at least the size of one arbitration-block on each of the switch. scala . Write Address Read Address Write Data Read Data Write Response Channel Channel Channel Channel Channel AWID ARID WID RID BID. AXI3 master . Upload File; Most Popular; Art & Photos; Automotive; Business; Career; Design; Education; Hi-TechJoins a read and a write slave into one single read / write master. CoreAXI4Interconnect is a configurable core with the following features: • Supports high-bandwidth and low-latency designs. master & slave : ERROR: svt_axi_checker: AMBA: AXI_ACE: perf_min_write_bandwidth_checkWrite-Write-Write-Write or Write-Read-Write-Read, etc. Write interleaving 1 2 1 Write interleaving depth = 1 X Write interleaving depth > 1 OK A B. pdf". Memory Interleaving is used to improve the access time of the main memory. 2. Tian Sheuan Chang Shared-link AXI provides decent communication performance and requires half the cost of its crossbar counterpart. There are a lot more interpretations of a BFM, BFMs typically reduce the job of a testbench by making it more data focused. That is not allowed with the addresses of 1,2,3. In AXI spec 1. 5. Abstract—this paper presents AMBA AXI-4, supports 16 masters and 16 slaves interfacing, with single master single slave talking to each other at a time. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol SpecificationLogiCORE IP AXI Interconnect v20 Product Guide for Vivado Design Suite PG059 March 20 2013 AXI Interconnect Product Guide v20 2 PG059 March 20 2013 Table of Contents…Interleaving reading and writing In general, a program performs both input and output and these are interleaved. . Read now: data analyst course in hyderabad. io and either CPI or AXI for CXL. newest, i read "AMBA® AXI Protocol. sv","contentType":"file"},{"name":"axi. The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. State why you are writing (i. between master and slave using a write data channel to the slave or a read data channel to the master. 1. Embed Size (px. point to point) scheme. Free essays, homework help, flashcards, research papers, book reports, term papers, history, science, politicsDMA RAM interface demultiplexer module for write operations. g. 19 March 2004 B Non-Confidential First release of AXI specification v1. Get the WDATA and AW together from the outstanding queue. I think data interleaving should not be done within a single burst. Following is my write channel code : // // File name: axi_mcb_w_channel. I have including seen many IP providers e. 1) A1 A2 B1 B2 (In-order)-> This is legal. g. erification of a. School of Engineering Science. PCIe AXI master module. It’s demanding work that helps make “long-term memory solid, problem solving easier, and mastery improve,” notes education consultant Margaret Searle. 1 Answer. WID is removed in AXI4, so WDATA must strictly follow the AW order. " Thanks in advance, Amaresh There is no write data interleaving in AXI4. 4. Issues B and C of this document included an AXI specification version, v1. I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid. While AXI4 props burst lengths of up the 256 beats. AMBA AXI and ACE Protocol Specification Version E. svt_axi_checker:: trace_tag_validity_check. in the. • The AXI SmartConnect core does not support discontinued AXI3 features: ° Atomic locked transactions: This feature was retracted by the AXI4 protocol. Chapter 4 Transfer Interleaving and Ordering Read this for a description of the stream interleaving and ordering restrictions. "For a slave that supports write data interleaving, the order that it receives the first data item of eachHowever, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. ° Supports write response re-ordering, Read data re-ordering, and Read Data interleaving. When 256 bits data is chosen in the GUI, this bus should be left undriven. To extend the read interleave question & assuming this use case only valid in AXI interconnect. I have and watch many IP providers e. 2 Write address channel signalsTable 2-2 lists the AXI write address channel signals. If the transmission unit is a block or packet. mapping the n word access ports to m interleaved banks. [1] [2] AXI has been introduced in 2003 with the AMBA3 specification. b). amba 3. although me have twos questions info AXI according hi. rtl/axi_axil_adapter_wr. By continuing to use our site. The data widths supported are: 32, 64, 128, 256, 512 and 1024. Module axi_to_mem_interleaved. 是否支持乱序只与slave有关，与master无关。. Various busses work various ways. Interrupt Out (To AXI Intc) Interrupt Out (To AXI Intc) AXI4. AxUSER, WUSER, RUSER, BUSER. address does not fall to correct interleaved port. In that case, I’ll want to assume the read channel is idle and remove the read channel cover check. While AXI4 supports burst lengths of up to 256 beats. When accessing a slave that supports write data interleaving, write data from different transactions that use the same AWID cannot be interleaved. AXI has the ability to issue multiple outstanding addresses and out-oforder transaction completion, but AXI has the ability of removal of locked transactions and write interleaving. sv","path":"src/axi_atop_filter. If two or four instances of the MC are selected, they are configured to form a single interleaved memory. By continuing to use our site, you consent to our cookies. 1. What is APB strobe? APB bridge. Under the Board page, make sure that both GPIO and GPIO2 are set to Custom. Also s_axi_awqos, s_axi_arqos, m_axi_awqos, m_axi_arqos are present, which should not be the case for AXI3, as. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. >Is it used only when we have multi-master cases? No. Typically, the read-modify-write operation can be achieved with a single atomic operation. 1. By disabling cookies, some features of the site will not workRead this chapter to learn about the AXI protocol architecture and the basic transactions that it defines. Hi, I'm a graduate student living in south Korea. As shown in FIG. 1 Answer. Tune for performance and re-simulate: Ensure that you have the right number of NoC NMUs and DDRMCs to meet your requirements. when i have two questions about1. Stage 2: Write Calibration Part One 1. By continuing to use our site, you consent to our cookies. For this the highest bits of the aw_id get pushed into a FIFO. when the WID is present in the old AXI version, a WDATA re-order mechanism will be inferred, and thanks to the remove of WID, we do not need that mechanism any longer. Loading Application. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed. An inherent requirement of the framebuffer streaming system is sufficient memory for storing intermediate frames. Re-ordering implies the transactions complete in a different order to that the AR channel transfers were completed, whereas interleaving suggests that more that one read data stream can be active, so data in successive transfers could be for different transactions. This specification defines the AMBA AXI-Stream protocols: • AXI4-Stream • AXI5-Stream The collective term AXI-Stream is used in instances that describes common features. , Simon Fraser University, 2010. Date post: 08-Sep-2020: Category: Documents: Author: others View: 23 times: Download: 1 times: Download Report this document. Pass condition: If trace_tag is set to. 深入理解AMBA总线（十一）AXI协议导论. Besides Cortex-A9 master there are the other masters (DMAC, PL AXI masters) and there are AXI interconnects, that are at the same time slaves and masters, and passes write data from multiple sources (slave. I'm research info AMBA 3. If yours DUT supports more than only simple write then you have to add other signals. Architecture AXI protocol is Burst-based transactions with only start address issued. DownsizerAxi is an AXI infrastructure component that enables you to connect a 64-bit AXI bus to a 32-bit AXI bus. i want to do random write transcation, and here is the waveform, does this waveform meets AXI spec. AXI3: Write data interleaving (for different IDs) is supported. I was going through write data interleaving section in ARM AXI3 protocol. Activity points. Table 43. 1) March 7, 2011. Select the IP Configuration page. The base addresses for slaves in the interconnect are also hence assigned in multiples of 4K. v under the block design in the sources window . This feature is not supported in AXI4 All Write Data for a transaction must be provided in consecutive transfers on the write data channel. Customize the PS to enable the AXI HP0 and AXI HP2 interface: Right-click the ZYNQ7 Processing System core and select Customize Block. * Supports write response reordering, Read data reordering, and Read Data interleaving. >In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave? First of all, an AXI4 master must not issue interleaved write data. 2. A. This site uses cookies to store information on your computer. AXI4 has removed the support for write data interleaving. The interval is specified in perf_recording_interval. This site uses cookies to store information on your computer. AXI_ERRM_WDATA_ORDER The order in which addresses and the first write data Write data interleaving on Page 8-6 item are produced must match. The interval is specified in perf_recording_interval. 4. wvalid { Write valid, this signal indicates that valid write data and strobes are available. One major up-dation seen in AXI is that, it includes information on the use of default signaling and discusses the interoperability of components which can’t be. Is it possible with single-master cases also?-> Yes. Performance constraint on the minimum expected bandwidth for write transfers in a given time interval. some will put the single word on a word sized bus and allow unaligned addresses. Of course it can have a larger addressing space, but again it has to be in the multiples of 4KB. CPUはコンピュータの動作に必要なデータや命令を 主記憶装置 とやり取りしながら処理します。. Synopsys. For example, we can access all four modules concurrently, obtaining parallelism. By disabling cookies, some features of the site will not workIn the waveform window, expand the write data channel of the m00_axi interface. Since AXI has 5 parallel channels running, many wires are used to lay the layout. 4 Standards Compliance The DW_axi_gs conforms to the AMBA 3 AXI and AMBA 4 AXI specifications defined in the AMBA AXI and ACE Protocol Specification from ARM. addressing space for any slave on AXI bus interconnect. import all of my_pkg into your testbench. AXI Master Configuration for ACP Access 10. September 1, 2014 at 6:53 PM AXI GP master and write data interleaving I'm designing AXI slave to connect it to Zynq AXI GP master and I'd like to know if AXI GP master can. [Chapter 8. uitable for. So for using this module it is recommended to extend each AXI ID by the required amount of bits indicating the index of the respective slave port, before being sent over this module. g. recently, i read "AMBA® AXI Protocol. Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive every clock cycle. the WDATA is not interleaving so the order of WDATA is the SAME witn the order of AW. Write transaction ID on the GIF is verified for write ID consistency between the AXI and the GIF without write interleaving or out-of-order write responses. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. g. AXI4 has removed the support for write data interleaving. . The problem I am facing is in AXI interface of MIG where 4-bit ID signal is present for all the transactiThis site uses cookies to store information on your computer. Figure 2-19: AXI Reference Guide UG761 (v13. 4. Upload File; Most Popular; Art & Photos; Automotive; Business; Career; Design; Education; Hi-TechYour commandline needs: +UVM_TESTNAME=apb_test. axi_rw_join and axi_rw_split to split/join the read and write channels of an AXI bus. Handle to transaction received from a master port. a. 一致性：所有接口子集都使用相同的传输协议。. The primary reason for removing WID was NOT to reduce the interface pin count, it was imply that the WID signal was no longer needed. Your write addresses are 1,2,3. If the particular slave. 3. Lowest Area. The AMBA AXI-4 system consists. by. v : AXI nonblocking crossbar interconnect rtl/axi. Master of Engineering Science. AXI Bus. Write interleave depth is a characteristic of the slave or the slave. If a slave does not support write data interleaving (see Write data interleaving on page 8-6), the master must issue the data of write transactions in the same order in which it issues the transaction addresses. but i saw AMBA 3. The new() function has two arguments as string name and uvm_component parent. Dec 17, 2021 at 19:03. Low-power Interface support; Atomic access support with normal access,exclusive access and locked access; AXI4 supportsvt_axi_system_transaction:: master_xact. Customize the AXI GPIO IP block:. In AXI4 we don't have write data interleaving, so if your master is issuing multiple write transactions using different IDs, there is a strict ordering requirement that all the WDATA transfers for the first issued AW channel transfer must be completed before any of the WDATA transfers for the second issued AW channel transfer. Intended audience This specification is written for hardware and softwa re engineers who want to become familiar with the Advanced Integrated Memory Controller . AXI Data Slave Interface. Synopsys supporting burst lengths up to 256 beats inbound AXI3 I have also seen many PROTECTION vendors. Your understanding is correct. The Read transaction ID (RID) provided by the HBM2 controller corresponds to the Read Address ID (ARID). of-order transaction completion, write and read data interleaving, separate read and write data channels, burst-based transactions with only start address issued and support for unaligned data transfers using byte strobes. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed. AXI Slave1 Write interleaving depth = 2 Bufferable Bit (Conti. Performance constraint on the minimum expected bandwidth for write transfers in a given time interval. Read transactions are handled similar to write transactions, except that before transferring the transaction to the AXI4 master read channel, the PCIESS checks the transmit buffer for available space. 1 Answer. 首页. 4 Normal write ordering. A master places an address on the AWADDR line and asserts a valid signal. 对于master，不建议发出out of order与interleaving的写数据，但是必须支持out of order与interleaving的读操作！这也是AXI4将wid去除的主要原因。 outstanding虽然好用，但是千万不能随便设置深度，一定要根据实际应用来设计，毕竟sram成本还是比较大的. All rights. To maintain uniformity in naming the components/objects, all the component/object name’s are starts with mem_ *. AXI is basically a multi-layer (i. 4x and 2. 1 PG059 April 5, 2017 89 Chapter 3: Designing with the Core AXI Downsizer The Width Conversion core performs a downsizer function whenever the data width on the SI side is wider than that on the MI side. Tune for performance and re-simulate: Ensure that you have the right number of NoC NMUs and DDRMCs to meet your requirements. 17. AXI4 supports QoS, AXI3 do NOT suppor QoS. Interface calibration and training information available through the Vivado hardware manager. This paper introduces the concept of multicluster interleaving (MCI), a. Check description: Trace tag value on data channel or resposne channel should be valid as per the trace tag. Since the scoreboard is a uvm_component. A master interface that is. it seems that my waveform does not meet the axi spec, because the awready can not always be 1 in rtl. AXI3 supports write interleaving. Synopsys NO supporting write interlock in AXI3. Migrating from AHB to AXI based SoC Designs This article describes the most important AMBA bus architectures and how they evolved to accommodate to the ever increasing complexity of SoC technology. m. • uses burst-based transactions with only the start address issued. I have seen many IP providers e. All rights reserved. Word count register – It contains the. AXI4 supports QoS, AXI3 does NOT support QoS. The AXI4-Lite Cross-bar interconnect is used to connect one or more AXI4-Lite compliant master devices to one or more AXI4-Lite compliant slave devices. For example if you would like to test read operation then you also have to add all signals. AXI4 supports QoS, AXI3 does NOT suppor QoS. Support for Read-only and Write-only master devices, resulting in reduced resource utilization. Found this statement: "For a slave that supports write data interleaving, the order in which it receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions. Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving: Multiple Read commands can be executed simultaneously and data interleaving is supported as long as all condition for ordering are followed. Enables sharing the PCIe AXI DMA module between multiple request sources, interleaving requests and distributing responses. Connected to axi bus ppt slideshareconfigured as AXI3 write data with interleaving (with write interleaving depth >1). • AXI4-Lite does not support data interleaving, the burst length is defined as 1 • AXI4-Lite supports multiple. This site uses cookies to store information on your computer. In VU+ HBM, there is a hardened AXI Switch which enables access from any of the 32 AXI channels to any of. Carries additional write data when AXI Data Width of 288-bits data is selected in the HBM2 IP GUI. The channels are Write address channel (AW), Write data channel (W), Read data channel aka R (Read response is sent with it as well), Read address channel (AR), and Write response channel (B). • Write data interleaving and write data Out-of-Order • Transaction with same ARID value to different slaves • Low-power interface of the AXI busAMBA3. When YUV, it has to write in the order: Cr Y Cb; Support frame buffer formats, including 1,2,4,8,16,24, and 32 bits per pixel. Write standard new() function. Out of order completion. Click. All five transaction channels use the same VALID/READY handshake processInterleaving allows you to send WID transfers for a number of outstanding AW transfers, BUT. Write interleave capability 1 No write interleaving is performed. Next Section. Submit the transaction. . 本系列的AXI文章不会像大部分科普文章简单翻译一下ARM文档，我会结合自己之前的设计经验、AXI背后的. No. By continuing to use our site, you consent to our cookies. {"payload":{"allShortcutsEnabled":false,"fileTree":{"AXI_Protocol/Design and Verification":{"items":[{"name":"AXI_Interface. The pcie_us_axi_master module is more complex, converting PCIe operations to AXI bursts. 12. No. Chapter 2 Signal Descriptions Refer to this chapter for definitions of the AXI global, write address channel, write data channel, write response channel, read address channel, read data channel, and low-power interface signals. By continuing to use our site, you consent to our cookies. - Read data of transactions with different ARID values can be interleaved. ° Write interleaving: This feature was retracted by AXI4 protocol. 11. , just a single interface between Master and Slave. It has been described as shown below. wvalid { Write valid, this signal indicates that valid write data and strobes are available. 1] AXI is a multi-channel bus with 5 independent channels like Write address channel, Read address channel, Write data channel, Read data channel, Write response channel (Read Response is sent. 19 March 2004 B Non-Confidential First release of AXI specification v1. And as section A5. axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and. Previous Section. mem_rdata_i: input mem_data_t [NumBanks-1:0] Memory stream. devices must be configured as if connected to a slave with a Write interleaving depth of one. The problem is with your combination of the write address and the write strobes. pdf". amba 3. Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec. Upload File; Most Popular; Art & Photos; Automotive; Business; Career; Home; Documents; AXI OverviewA multi-channel DDR interleaving control method and device, and a storage medium. 6. The first 1, 2 and 3 byte strobes must be zero because you address is skipping those. This covergroup is hit when address phase completion of four transactions are observed in a specific combination as described above. apb_test doesn't extend from uvm_test. The data widths supported are: 32, 64, 128, 256, 512 and 1024. This specification defines the AMBA AXI-Stream protocols: • AXI4-Stream • AXI5-Stream The collective term AXI-Stream is used in instances that describes common features. 如图所示，slave在返回了一个RID为ID2. AXI3 carries locked transfers, AXI4 does NON support locked transfers. Write buffer between stage 1 and 2 to store interleaving write packets Parameters of AXI4[-Stream] protocol can be adjusted in AXI4. But it's not the only possible source of interleaved write data. Examples: see 1) 2) 3) below. 1) I would like to know how read and write address requests issued to slave are associated with read or write data. AXI4 接口的主要优势. In this case, instead of waiting for one sequence to complete before the other sequence start, the AXI infrastructure can interleave the write. These features enable the implementation of high-performance interconnect, maximising data throughput and system efficiency. . Is it . By interleaving the two write data streams, the interconnect can improve system performance. 2. This document gives explanation about Cortex-A9 AXI masters. Memory Interleaving is used to improve the access time of the main memory.